1. Field
The exemplary embodiments relate to a memory device and a method for driving the same.
2. Description of the Prior Art
A semiconductor memory device, such as a DRAM (Dynamic Random Access Memory), has been continuously developed in order to increase the integrity thereof and to improve the operating speed thereof. In order to improve the operating speed of the DRAM, an SDRAM (Synchronous Dynamic Random Access Memory), which can operate in synchronization with an external clock signal that is input from an outside, has developed.
However, the SDRAM is insufficient to meet the speed of a system that requires high-speed operation. Accordingly, a DDR (Double Data Rate) RAM, which corresponds to a method of processing two sets of data in one clock cycle, has been proposed. The DDR RAM can successively input and output two sets of data in synchronization with a rising edge and a falling edge of an external clock signal that is input from the outside, and thus can perform high-speed operation.
On the other hand, the DDR RAM has been developed to “DDR2 SDRAM,” “DDR3 SDRAM,” and “DDR4 SDRAM” through generational changes. DDR2 SDRAM allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus. DDR3 SDRAM has twice the data rate of DDR2 SDRAM. DDR4 SDRAM has a high bandwidth interface. DDR4 SDRAM has faster clock frequencies and data transfer rates than DDR3 SDRAM, while the current remains the same.